A cache memory is a supplemental, smaller memory unit that is positioned in the memory hierarchy between the CPU and a slower memory in a digital computer. One goal of use of a cache memory is to improve effective memory transfer rates and thus raise processor speeds for the computer itself. A cache memory is usually hidden and appears to be transparent to the computer user, who is only aware of the apparently higher speed of response of the computer main memory. The cache memory may be implemented by semiconductor devices whose speeds are comparable with that of the CPU itself, although the main memory utilizes less costly, lower speed semiconductor devices. Ideally, the cache memory contains only data that are most likely to be reused (many times) by the CPU in its operations. Because most data in the disc memory of a computer are not used many times before being modified or replaced by other data, the size of the cache memory may be made much smaller than the size of the memory.
The use of higher speed semiconductor devices in the cache memory, plus the smaller size of the cache memory relative to the disc memory, insure that searches for particular, multiply-used data will be completed much faster in cache memory then in the disc memory. The data in the cache memory may be updated each time the corresponding data in disc memory are updated so that little or no time is lost in the overwriting process. Some of the initial cache memories were of limited size (32K bytes available in the IBM 360/195 and 2K bytes in the DEC 11/70 system), but no intrinsic limits exist for the size of cache memory.
Introduction of cache memory techniques in disk drive controllers has resulted in a substantial improvement in controller system performance figures; controller speed has increased by a factor of 2-4, depending upon the bench mark test used. Even a gain in speed by a factor of 2 represents an attractive gain in the performance-cost ratio at the system level. However, use of cache techniques has led to a inclusion of greater amounts of computational power in the controller itself. Cache management requires extensive processing within the system and has sometimes led to the use of two processors to achieve the necessary real time performance. Even where dual processors are used, detection of a cache "hit" (finding a chosen data word in cache memory before beginning the lengthier search in disc memory) and subsequent transfer of the chosen data word to the host computer requires about 3 msec for 2048 bytes of data. Use of firmware techniques in a fully associative cache memory may require time intervals up to 1 msec for detection of a hit using 512 cache buffers that each contain a data word. The invention disclosed herein can determine if a chosen data word is contained in cache memory and identify the data word pointer to the appropriate memory space in about 1.9 .mu.sec when the system is clocked at a minimum cycle time of 50 nsec.